Laser diodes for pico-projector applications are conventionally driven through a programmable current source, e.g. a DAC. Rise/fall times and settling time of an output current are comprised in parameters that may be used to define the quality of the projection, and designing the DACs in order to meet these specifications is desired.
Conventional DAC circuits may comprise multiple output current terminals, e.g. a positive and negative output terminal, which may be controlled by corresponding switching transistors, which may selectively couple the output current terminals to a current source, e.g. cascoded current source transistors. The switching transistors may be selectively activated and deactivated, by means of a digital control signal, to provide current at the positive and negative output terminals.
The switching transistors may selectively couple the positive and negative output terminals to the current source, e.g. through a common node.
It has been observed that such conventional circuits, however, may exhibit one or more of the following drawbacks:                the control terminals (e.g. gates) of the current source transistors may require a constant bias voltage applied thereto, thereby keeping a constant current flow,        if both the switching transistors are simultaneously OFF, the common node connecting the current paths of the switching transistors is (rapidly) discharged and it may require a non-negligible period of time to recharge; accordingly, the switching transistors are driven in order to avoid that both switching transistors are simultaneously off,        there is a constant DC power dissipation, and/or        turn on/off of the switching transistors may cause a glitch in the output current, due to stray capacitances active between the control terminal of each switching transistor and the corresponding output terminal coupled thereto, e.g. between gate and drain in case of MOSFET switching transistors.        
Such a conventional circuit was modified, and further solutions are known for example from document H. Takakura et al.: “A 10 bit 80 MHz glitchless CMOS D/A converter”, IEEE, 1991, Custom Integrated Circuits Conf. (CICC), incorporated by reference. It was observed that the solution disclosed by Takakura, comprising switching transistors, aims to reduce a current feedthrough occurring, due to the stray capacitances, between the control terminals of the switching transistors and corresponding output terminals coupled to the switching transistors. Also, a reduction of switching noise caused by the switching transistors may be achieved and a settling time of the DAC converter may be improved. However, it was observed that the solution may lead to a reduced output voltage swing.
Also, U.S. Pat. No. 7,138,855 (EP 1366568 B1), incorporated by reference, teaches a circuit where, during power-off transients of an output current, a stray capacitance may couple a step-down voltage to a node coupled to a current source transistor. In such case, the step-down voltage increases a voltage regulating the current passing through the current source transistor (e.g. increases the gate-source voltage in case of FET transistors) and produces a spike in the output current, with the generated spike in the current that discharges the stray capacitance.
U.S. Pat. No. 7,138,855 aims at providing an improved solution with respect to circuits according to the prior art, for switching a current off without inducing an overcurrent event and discloses, in order to reduce occurrence of overcurrent, an arrangement wherein a switch is introduced parallel to the capacitance, which, if active, short circuits and discharges the stray capacitance. The discharge current, therefore, does no longer produce a current spike in the output current and is not transmitted to a load.
Also, if the bias voltage applied to the control terminal of the current source transistor is lower than the sum of the threshold voltages of the current source transistor and a switching transistor, then the voltage regulating the current passing through the switching transistor (e.g. the gate-source voltage thereof) may reach the threshold voltage, and if such voltage is lower than the threshold voltage of the switching transistor then the current source transistor switches off.
Ka-Hou Ao Leong et al., “Design of a 1-V 10-bit 120-MS/s Current-Streering DAC with Transient-Improved Technique”, RIUPEEEC, 2006, incorporated by reference, discloses a cascode-switch current source (CSCS) circuit. The Leong reference aims at reducing a distortion which may be due to a falling settling time being different than a rising settling time for an output current. It was observed that:                when the switching transistors present in the document are off, respective nodes, coupled to their current paths, may be exponentially charged until further transistors, similarly coupled to the respective nodes, enter in the subthreshold region;        stray capacitances may be also present at the respective nodes, which may further extend the transient(s); and        a Charge-Removal-Replacement (CRR) topology provides the charge that may be required to settle faster the respective nodes.        
Also, it was observed that one or more timing advantages due to a better settling of the node may be present, e.g.:                a balanced speed and advanced transition: due to the absence of an exponential discharge for the cascode, a balanced falling and rising speed may be obtained;        recovered synchronization for each current source: the respective nodes may require same settling time (charging time) during each clock cycle, thus no delay difference among active current paths and no input-data-dependent non-linearity are present; and        susceptibility to asynchronous glitches may decrease.        
However, it was observed that the circuit may exhibit one or more disadvantages, e.g. precise CRR capacitances may be desired.
Further DAC circuits were observed, for example a circuit exemplified in document U.S. Pat. No. 5,548,238, incorporated by reference, which aims at reducing consumption in idle mode. In conventional DACs, an idle current is steered to ground, thereby leading to a high power consumption in idle mode. In the document, however, the current path may be switched off, thereby possibly achieving no power consumption in idle mode.
In the exemplified DAC, it may be possible to turn on a current source transistor in order to establish a stable current and to bias all the nodes related thereto, before turning to an “on” mode the DAC. In order to achieve a smooth transition, the current steering circuitry may be turned to the “on” mode after the current source transistor is turned on.
Conversely, the transition from “on” to “off” mode is achieved by first steering the current to ground and then cutting off the current source transistor.
It was also observed that two capacitors may be introduced in the DAC circuit, in order to compensate the distortion on the bias voltages caused by coupling with stray capacitors (e.g. stray capacitors between drain and gate of MOSFET transistors, e.g. the current source transistor) during the current source switching.